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| author |   Caz Yokoyama <caz.yokoyama@intel.com> | 2022-03-30 08:57:23 -0700 |
|---|---|---|
| committer |   José Roberto de Souza <jose.souza@intel.com> | 2022-03-30 13:34:46 -0700 |
| commit | 291f63e72e56a6433910d80e23da384c62077538 (patch) | |
| tree | dd0de51ad508236b20fa6df82975f2868f8f9aed /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL (diff) | |
| download | wireguard-linux-291f63e72e56a6433910d80e23da384c62077538.tar.xz wireguard-linux-291f63e72e56a6433910d80e23da384c62077538.zip | |
drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
Alderlake-P has different MBUS DBOX BW and B credits than other
platforms, so here setting it properly.
BSpec: 49213
BSpec: 50343
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions