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| author |   Imre Deak <imre.deak@intel.com> | 2022-02-22 18:51:30 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-02-28 17:03:32 +0200 |
| commit | 492c1ae2f27c327ef8d0f2019cac66408a41d808 (patch) | |
| tree | 884d0a945441044b77123d00f73eac062de10c1b /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915/wm: use REG_FIELD_{PREP,GET} for PLANE_WM_BLOCKS_MASK (diff) | |
| download | wireguard-linux-492c1ae2f27c327ef8d0f2019cac66408a41d808.tar.xz wireguard-linux-492c1ae2f27c327ef8d0f2019cac66408a41d808.zip | |
drm/i915: Fix the VDSC_PW2 power domain enum value
The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.
While at it add a code comment about enum values that need to stay
consecutive.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-2-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions