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| author |   Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-05-10 10:57:06 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-05-11 12:27:27 +0100 |
| commit | 7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba (patch) | |
| tree | 9e6cb09c120d1658e07c4a1deaae613cdb3d8fcc /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Promote IS_BROADWELL to a simple macro (diff) | |
| download | wireguard-linux-7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba.tar.xz wireguard-linux-7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba.zip | |
drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx
This way optimization from a previous patch works even better.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e17a682dd621..84b22a57cc1c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2503,7 +2503,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) * the semaphore value, then when the seqno moves backwards all * future waits will complete instantly (causing rendering corruption). */ - if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { + if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev_priv)) |