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| author |   Durgadoss R <durgadoss.r@intel.com> | 2015-03-27 17:21:32 +0530 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-30 16:39:31 +0200 |
| commit | 670b90d20a5d71a2f430e0c4b97dac2d17a659b5 (patch) | |
| tree | e33e130569f90c21d36891563fa40d68556bca77 /drivers/gpu/drm/i915/intel_sdvo.c | |
| parent | Enabled dithering in the intel VCH DVO for 18bpp pipelines. (diff) | |
| download | wireguard-linux-670b90d20a5d71a2f430e0c4b97dac2d17a659b5.tar.xz wireguard-linux-670b90d20a5d71a2f430e0c4b97dac2d17a659b5.zip | |
drm/i915: PSR: Keep sink state consistent with source
BSpec recommends to keep the main link state consistent
between the source and the sink. As per that, update
the main link state in sink DPCD register to 'active',
for Valleyview based platforms.
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo.c')
0 files changed, 0 insertions, 0 deletions