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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-31 14:09:47 +0300 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-31 17:28:40 +0200 |
| commit | e907f1704c402122b0c0a206d8064e19b79ed1c3 (patch) | |
| tree | 251ae4f91394fcb68ef346afb8797a10a0497634 /drivers/gpu/drm/i915/intel_sdvo.c | |
| parent | drm/i915: Enable DVO 2x clock around DVO encoder init (diff) | |
| download | wireguard-linux-e907f1704c402122b0c0a206d8064e19b79ed1c3.tar.xz wireguard-linux-e907f1704c402122b0c0a206d8064e19b79ed1c3.zip | |
drm/i915: Return more precise cdclk for gen2/3
Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's
not clear if these are accurate frquencies or just in the ballpark, but
without docs this is the best we can do.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo.c')
0 files changed, 0 insertions, 0 deletions