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| author |   José Roberto de Souza <jose.souza@intel.com> | 2018-10-03 13:50:26 -0700 |
|---|---|---|
| committer |   Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-10-05 16:10:52 -0700 |
| commit | fc6ff9dc9ecf7e10597a85c4b83c304fb7c7083e (patch) | |
| tree | 1dc0b1f49bb846510dde68e11945b3fa5219cdbd /drivers/gpu/drm/i915/intel_sprite.c | |
| parent | drm/i915/psr: Share PSR and PSR2 exit mask (diff) | |
| download | wireguard-linux-fc6ff9dc9ecf7e10597a85c4b83c304fb7c7083e.tar.xz wireguard-linux-fc6ff9dc9ecf7e10597a85c4b83c304fb7c7083e.zip | |
drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
ICL spec states that this bit is now reserved.
Bspec: 7722
v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003205031.32474-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
0 files changed, 0 insertions, 0 deletions