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| author |   Julien Masson <jmasson@baylibre.com> | 2019-06-24 16:47:56 +0200 |
|---|---|---|
| committer |   Neil Armstrong <narmstrong@baylibre.com> | 2019-08-09 11:37:30 +0200 |
| commit | f237bf2de82eafd224eb981c6c0bca8a9e039af6 (patch) | |
| tree | 46e4685bfc08a2c8f759a81596e97e89badb5ad0 /drivers/gpu/drm/meson/meson_vpp.c | |
| parent | drm/panel: simple: Support TI nspire panels (diff) | |
| download | wireguard-linux-f237bf2de82eafd224eb981c6c0bca8a9e039af6.tar.xz wireguard-linux-f237bf2de82eafd224eb981c6c0bca8a9e039af6.zip | |
drm: meson: mask value when writing bits relaxed
The value used in the macro writel_bits_relaxed has to be masked since
we don't want change the bits outside the mask.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86y31r82fo.fsf@baylibre.com
Diffstat (limited to 'drivers/gpu/drm/meson/meson_vpp.c')
0 files changed, 0 insertions, 0 deletions