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| author |   Dmitry Osipenko <digetx@gmail.com> | 2021-09-30 01:28:05 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2021-12-16 14:07:07 +0100 |
| commit | 0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c (patch) | |
| tree | 503f22db3d777e19cdf04663606a6e66ded1f103 /drivers/gpu/drm/tegra/dc.h | |
| parent | drm/tegra: Remove duplicate struct declaration (diff) | |
| download | wireguard-linux-0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c.tar.xz wireguard-linux-0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c.zip | |
drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+
Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI
bridge that requires a precise clock rate in order to operate properly.
Tegra30 has a dedicated PLL for each display controller, hence the PLL
rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB
output. Configure the clock rate before display controller is enabled
since DC itself may be running off this PLL and it's not okay to change
the rate of the active PLL that doesn't support dynamic frequency
switching since hardware will hang.
Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 40378308d527..c9c4c45c0518 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -76,6 +76,7 @@ struct tegra_dc_soc_info { bool has_win_b_vfilter_mem_client; bool has_win_c_without_vert_filter; bool plane_tiled_memory_bandwidth_x2; + bool has_pll_d2_out0; }; struct tegra_dc { |