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| author |   Dmitry Osipenko <digetx@gmail.com> | 2021-12-01 02:23:18 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2021-12-16 14:07:07 +0100 |
| commit | 4ce3048c0a622978436e04b47eade8c45e1e8a75 (patch) | |
| tree | dbe1de89316b6439dcc7872eff5902a63009888a /drivers/gpu/drm/tegra/dc.h | |
| parent | drm/tegra: submit: Add missing pm_runtime_mark_last_busy() (diff) | |
| download | wireguard-linux-4ce3048c0a622978436e04b47eade8c45e1e8a75.tar.xz wireguard-linux-4ce3048c0a622978436e04b47eade8c45e1e8a75.zip | |
drm/tegra: dc: Support OPP and SoC core voltage scaling
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index c9c4c45c0518..3f91a10ea6c7 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -101,6 +101,8 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + bool has_opp_table; }; static inline struct tegra_dc * |