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| author |   Thierry Reding <treding@nvidia.com> | 2015-04-27 14:48:35 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-13 13:47:43 +0200 |
| commit | 8fd3ffa902a0d9f282ffa80599970ff1c823b1a8 (patch) | |
| tree | a116aa9be3741bcbe07fbf6f0eefd3f8c137303e /drivers/gpu/drm/tegra/dc.h | |
| parent | drm/tegra: dc: Record statistics (diff) | |
| download | wireguard-linux-8fd3ffa902a0d9f282ffa80599970ff1c823b1a8.tar.xz wireguard-linux-8fd3ffa902a0d9f282ffa80599970ff1c823b1a8.zip | |
drm/tegra: dc: Rename register for consistency
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 5edae2653f09..87700bf60108 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -119,9 +119,9 @@ #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 -#define H_PULSE_0_ENABLE (1 << 8) -#define H_PULSE_1_ENABLE (1 << 10) -#define H_PULSE_2_ENABLE (1 << 12) +#define H_PULSE0_ENABLE (1 << 8) +#define H_PULSE1_ENABLE (1 << 10) +#define H_PULSE2_ENABLE (1 << 12) #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 |