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| author |   Thierry Reding <treding@nvidia.com> | 2014-06-03 14:48:12 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-08-04 10:07:34 +0200 |
| commit | c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8 (patch) | |
| tree | 0d26c79eefb921fd0841b9d48c48b589a3ad2f8a /drivers/gpu/drm/tegra/dc.h | |
| parent | drm/tegra: dsi - Handle non-continuous clock flag (diff) | |
| download | wireguard-linux-c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8.tar.xz wireguard-linux-c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8.zip | |
drm/tegra: Implement more tiling modes
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 78c5feff95d2..705c93b00794 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -428,6 +428,11 @@ #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 #define DC_WINBUF_UFLOW_STATUS 0x80a +#define DC_WINBUF_SURFACE_KIND 0x80b +#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) +#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) +#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) +#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) #define DC_WINBUF_AD_UFLOW_STATUS 0xbca #define DC_WINBUF_BD_UFLOW_STATUS 0xdca |