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| author |   Thierry Reding <treding@nvidia.com> | 2021-05-27 20:15:46 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-05-31 14:30:11 +0200 |
| commit | e16efff4e5f490ce34a8c60d9ae7297dca5eb616 (patch) | |
| tree | 62b017c665cdbdbeae4f9b286b86af62b92990e6 /drivers/gpu/drm/tegra/dc.h | |
| parent | drm/tegra: Correct DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT (diff) | |
| download | wireguard-linux-e16efff4e5f490ce34a8c60d9ae7297dca5eb616.tar.xz wireguard-linux-e16efff4e5f490ce34a8c60d9ae7297dca5eb616.zip | |
drm/tegra: hub: Fix YUV support
The driver currently exposes several YUV formats but fails to properly
program all the registers needed to display such formats. Add the right
programming sequences so that overlay windows can be used to accelerate
color format conversions in multimedia playback use-cases.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 29f19c3c6149..455c3fdef8dc 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -696,6 +696,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WINBUF_START_ADDR_HI 0x80d +#define DC_WINBUF_START_ADDR_HI_U 0x80f +#define DC_WINBUF_START_ADDR_HI_V 0x811 + #define DC_WINBUF_CDE_CONTROL 0x82f #define ENABLE_SURFACE (1 << 0) @@ -720,6 +723,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define DC_WIN_PLANAR_STORAGE 0x709 #define PITCH(x) (((x) >> 6) & 0x1fff) +#define DC_WIN_PLANAR_STORAGE_UV 0x70a +#define PITCH_U(x) ((((x) >> 6) & 0x1fff) << 0) +#define PITCH_V(x) ((((x) >> 6) & 0x1fff) << 16) + #define DC_WIN_SET_PARAMS 0x70d #define CLAMP_BEFORE_BLEND (1 << 15) #define DEGAMMA_NONE (0 << 13) |