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authorDavid Box <david.e.box@linux.intel.com>2015-01-15 01:12:17 -0800
committerWolfram Sang <wsa@the-dreams.de>2015-01-26 12:26:25 +0100
commit894acb2f823b13afacfe40b02efbd9146af58586 (patch)
tree0f4b01bb796bfbceaf1764111a356581502bedcd /drivers/i2c/busses/i2c-designware-core.h
parenti2c: designware: Add i2c bus locking support (diff)
downloadwireguard-linux-894acb2f823b13afacfe40b02efbd9146af58586.tar.xz
wireguard-linux-894acb2f823b13afacfe40b02efbd9146af58586.zip
i2c: designware: Add Intel Baytrail PMIC I2C bus support
This patch implements an I2C bus sharing mechanism between the host and platform hardware on select Intel BayTrail SoC platforms using the X-Powers AXP288 PMIC. On these platforms access to the PMIC must be shared with platform hardware. The hardware unit assumes full control of the I2C bus and the host must request access through a special semaphore. Hardware control of the bus also makes it necessary to disable runtime pm to avoid interfering with hardware transactions. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses/i2c-designware-core.h')
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index ef8ba839e2d3..9630222abf32 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -125,3 +125,9 @@ extern void i2c_dw_disable(struct dw_i2c_dev *dev);
extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
+
+#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
+extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
+#else
+static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
+#endif