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| author |   Robin Murphy <robin.murphy@arm.com> | 2017-06-22 16:53:50 +0100 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2017-06-23 17:57:58 +0100 |
| commit | 9db829d2818501f07583542c05d01513b9161e14 (patch) | |
| tree | c5e18068241aabedc88d216f2526daf5b148d4de /drivers/iommu | |
| parent | iommu: arm-smmu: Handle return of iommu_device_register. (diff) | |
| download | wireguard-linux-9db829d2818501f07583542c05d01513b9161e14.tar.xz wireguard-linux-9db829d2818501f07583542c05d01513b9161e14.zip | |
iommu/io-pgtable-arm-v7s: Check table PTEs more precisely
Whilst we don't support the PXN bit at all, so should never encounter a
level 1 section or supersection PTE with it set, it would still be wise
to check both table type bits to resolve any theoretical ambiguity.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/io-pgtable-arm-v7s.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c index f8869951610c..46da7aa7c7d0 100644 --- a/drivers/iommu/io-pgtable-arm-v7s.c +++ b/drivers/iommu/io-pgtable-arm-v7s.c @@ -92,7 +92,8 @@ #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) -#define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE)) +#define ARM_V7S_PTE_IS_TABLE(pte, lvl) \ + ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE)) /* Page table bits */ #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) |