diff options
| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2024-02-13 18:12:31 +0000 |
|---|---|---|
| committer |   Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2024-02-15 10:57:54 +0100 |
| commit | 276739485501e61096034ec036337feab4c07dc5 (patch) | |
| tree | 0eb0a3b94c50d34ef3fcf65dec94335e47d8ea83 /drivers/media/platform | |
| parent | media: platform: rzg2l-cru: rzg2l-ip: Add delay after D-PHY reset (diff) | |
| download | wireguard-linux-276739485501e61096034ec036337feab4c07dc5.tar.xz wireguard-linux-276739485501e61096034ec036337feab4c07dc5.zip | |
media: platform: rzg2l-cru: rzg2l-video: Fix image processing initialization
As per section 35.3.1 Starting Reception for the MIPI CSI-2 Input on the
latest hardware manual (R01UH0914EJ0140 Rev.1.40) it is mentioned that
initialize the AXI master first and then initialize the image processing.
Fix the start procedure as per the hardware manual.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20240213181233.242316-4-biju.das.jz@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'drivers/media/platform')
| -rw-r--r-- | drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c index d0ffa90bc656..a7d6fe831d54 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -430,13 +430,6 @@ int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru) spin_lock_irqsave(&cru->qlock, flags); - /* Initialize image convert */ - ret = rzg2l_cru_initialize_image_conv(cru, fmt); - if (ret) { - spin_unlock_irqrestore(&cru->qlock, flags); - return ret; - } - /* Select a video input */ rzg2l_cru_write(cru, CRUnCTRL, CRUnCTRL_VINSEL(0)); @@ -450,6 +443,13 @@ int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru) /* Initialize the AXI master */ rzg2l_cru_initialize_axi(cru); + /* Initialize image convert */ + ret = rzg2l_cru_initialize_image_conv(cru, fmt); + if (ret) { + spin_unlock_irqrestore(&cru->qlock, flags); + return ret; + } + /* Enable interrupt */ rzg2l_cru_write(cru, CRUnIE, CRUnIE_EFE); |