diff options
| author |   Carolina Jubran <cjubran@nvidia.com> | 2025-09-03 10:30:00 +0300 |
|---|---|---|
| committer |   Leon Romanovsky <leon@kernel.org> | 2025-09-09 04:18:19 -0400 |
| commit | ff97bc38be343e4530e2f140b40cbdce2e09152f (patch) | |
| tree | a40510eb04a01fd30a0dee33f2e9dcecdb6a5977 /drivers/net/dsa/dsa_loop.c | |
| parent | net/mlx5: Add PSP capabilities structures and bits (diff) | |
| download | wireguard-linux-ff97bc38be343e4530e2f140b40cbdce2e09152f.tar.xz wireguard-linux-ff97bc38be343e4530e2f140b40cbdce2e09152f.zip | |
net/mlx5: Add RS FEC histogram infrastructure
Define the Ports Phy Histogram Configuration Register (PPHCR) to expose
RS-FEC histogram bin ranges, and expose a new counter group in the Ports
Performance Counters Register (PPCNT) to report the corresponding
histogram values.
Co-developed-by: Yael Chemla <ychemla@nvidia.com>
Signed-off-by: Yael Chemla <ychemla@nvidia.com>
Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1756884600-520195-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Diffstat (limited to 'drivers/net/dsa/dsa_loop.c')
0 files changed, 0 insertions, 0 deletions