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authorVladimir Oltean <vladimir.oltean@nxp.com>2022-05-22 00:37:41 +0300
committerDavid S. Miller <davem@davemloft.net>2022-05-23 10:39:54 +0100
commit8c166acb60f8284470db673b6dccd43e6fedfae2 (patch)
treec8fc86285ba753e8b153d3e8d26dd6c5534a3ec2 /drivers/net/dsa/ocelot/felix.c
parentnet: dsa: felix: update bridge fwd mask from ocelot lib when changing tag_8021q CPU (diff)
downloadwireguard-linux-8c166acb60f8284470db673b6dccd43e6fedfae2.tar.xz
wireguard-linux-8c166acb60f8284470db673b6dccd43e6fedfae2.zip
net: dsa: felix: directly call ocelot_port_{set,unset}_dsa_8021q_cpu
Absorb the final details of calling ocelot_port_{,un}set_dsa_8021q_cpu(), i.e. the need to lock &ocelot->fwd_domain_lock, into the callee, to simplify the caller and permit easier code reuse later. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/ocelot/felix.c')
-rw-r--r--drivers/net/dsa/ocelot/felix.c36
1 files changed, 9 insertions, 27 deletions
diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index b60d6e7295e1..033f7d5cc03d 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -240,31 +240,6 @@ static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
return 0;
}
-/* Alternatively to using the NPI functionality, that same hardware MAC
- * connected internally to the enetc or fman DSA master can be configured to
- * use the software-defined tag_8021q frame format. As far as the hardware is
- * concerned, it thinks it is a "dumb switch" - the queues of the CPU port
- * module are now disconnected from it, but can still be accessed through
- * register-based MMIO.
- */
-static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port)
-{
- mutex_lock(&ocelot->fwd_domain_lock);
-
- ocelot_port_set_dsa_8021q_cpu(ocelot, port);
-
- mutex_unlock(&ocelot->fwd_domain_lock);
-}
-
-static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port)
-{
- mutex_lock(&ocelot->fwd_domain_lock);
-
- ocelot_port_unset_dsa_8021q_cpu(ocelot, port);
-
- mutex_unlock(&ocelot->fwd_domain_lock);
-}
-
static int felix_trap_get_cpu_port(struct dsa_switch *ds,
const struct ocelot_vcap_filter *trap)
{
@@ -423,6 +398,13 @@ static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds)
return BIT(ocelot->num_phys_ports);
}
+/* Alternatively to using the NPI functionality, that same hardware MAC
+ * connected internally to the enetc or fman DSA master can be configured to
+ * use the software-defined tag_8021q frame format. As far as the hardware is
+ * concerned, it thinks it is a "dumb switch" - the queues of the CPU port
+ * module are now disconnected from it, but can still be accessed through
+ * register-based MMIO.
+ */
static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = {
.setup = felix_tag_npi_setup,
.teardown = felix_tag_npi_teardown,
@@ -440,7 +422,7 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds)
return err;
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
- felix_8021q_cpu_port_init(ocelot, cpu_dp->index);
+ ocelot_port_set_dsa_8021q_cpu(ocelot, cpu_dp->index);
/* TODO we could support multiple CPU ports in tag_8021q mode */
break;
@@ -490,7 +472,7 @@ static void felix_tag_8021q_teardown(struct dsa_switch *ds)
}
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
- felix_8021q_cpu_port_deinit(ocelot, cpu_dp->index);
+ ocelot_port_unset_dsa_8021q_cpu(ocelot, cpu_dp->index);
/* TODO we could support multiple CPU ports in tag_8021q mode */
break;