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| author |   Aya Levin <ayal@mellanox.com> | 2020-08-12 10:44:36 +0300 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2020-10-02 10:59:57 -0700 |
| commit | 2608a2f831c47dfdf18885a7289be5af97182b05 (patch) | |
| tree | 0700f79971ddcacc9bb0dd54e80e074e036f40fa /drivers/net/ethernet/mellanox/mlx5/core/en/port.c | |
| parent | net/mlx5e: Fix driver's declaration to support GRE offload (diff) | |
| download | wireguard-linux-2608a2f831c47dfdf18885a7289be5af97182b05.tar.xz wireguard-linux-2608a2f831c47dfdf18885a7289be5af97182b05.zip | |
net/mlx5e: Fix return status when setting unsupported FEC mode
Verify the configured FEC mode is supported by at least a single link
mode before applying the command. Otherwise fail the command and return
"Operation not supported".
Prior to this patch, the command was successful, yet it falsely set all
link modes to FEC auto mode - like configuring FEC mode to auto. Auto
mode is the default configuration if a link mode doesn't support the
configured FEC mode.
Fixes: b5ede32d3329 ("net/mlx5e: Add support for FEC modes based on 50G per lane links")
Signed-off-by: Aya Levin <ayal@mellanox.com>
Reviewed-by: Eran Ben Elisha <eranbe@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/port.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en/port.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c index 96608dbb9314..308fd279669e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c @@ -569,6 +569,9 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy) if (fec_policy >= (1 << MLX5E_FEC_LLRS_272_257_1) && !fec_50g_per_lane) return -EOPNOTSUPP; + if (fec_policy && !mlx5e_fec_in_caps(dev, fec_policy)) + return -EOPNOTSUPP; + MLX5_SET(pplm_reg, in, local_port, 1); err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0); if (err) |