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| author |   Andre Przywara <andre.przywara@arm.com> | 2020-03-24 13:23:45 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-03-24 16:33:05 -0700 |
| commit | 4e958f33ee8f404787711416fe0f78cce2b2f4e2 (patch) | |
| tree | 7e21b924ac3879690f66fd97bf2579295660e5df /drivers/net/ethernet/xilinx/xilinx_axienet.h | |
| parent | net: axienet: Wrap DMA pointer writes to prepare for 64 bit (diff) | |
| download | wireguard-linux-4e958f33ee8f404787711416fe0f78cce2b2f4e2.tar.xz wireguard-linux-4e958f33ee8f404787711416fe0f78cce2b2f4e2.zip | |
net: axienet: Upgrade descriptors to hold 64-bit addresses
Newer revisions of the AXI DMA IP (>= v7.1) support 64-bit addresses,
both for the descriptors itself, as well as for the buffers they are
pointing to.
This is realised by adding "MSB" words for the next and phys pointer
right behind the existing address word, now named "LSB". These MSB words
live in formerly reserved areas of the descriptor.
If the hardware supports it, write both words when setting an address.
The buffer address is handled by two wrapper functions, the two
occasions where we set the next pointers are open coded.
For now this is guarded by a flag which we don't set yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/xilinx/xilinx_axienet.h')
| -rw-r--r-- | drivers/net/ethernet/xilinx/xilinx_axienet.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index fb7450ca5c53..84c4c3655516 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -328,6 +328,7 @@ #define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1) #define XAE_FEATURE_FULL_RX_CSUM (1 << 2) #define XAE_FEATURE_FULL_TX_CSUM (1 << 3) +#define XAE_FEATURE_DMA_64BIT (1 << 4) #define XAE_NO_CSUM_OFFLOAD 0 @@ -340,9 +341,9 @@ /** * struct axidma_bd - Axi Dma buffer descriptor layout * @next: MM2S/S2MM Next Descriptor Pointer - * @reserved1: Reserved and not used + * @next_msb: MM2S/S2MM Next Descriptor Pointer (high 32 bits) * @phys: MM2S/S2MM Buffer Address - * @reserved2: Reserved and not used + * @phys_msb: MM2S/S2MM Buffer Address (high 32 bits) * @reserved3: Reserved and not used * @reserved4: Reserved and not used * @cntrl: MM2S/S2MM Control value @@ -355,9 +356,9 @@ */ struct axidma_bd { u32 next; /* Physical address of next buffer descriptor */ - u32 reserved1; + u32 next_msb; /* high 32 bits for IP >= v7.1, reserved on older IP */ u32 phys; - u32 reserved2; + u32 phys_msb; /* for IP >= v7.1, reserved for older IP */ u32 reserved3; u32 reserved4; u32 cntrl; |