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| author |   Rob Herring <robh@kernel.org> | 2020-08-20 21:53:44 -0600 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-09-08 16:36:50 +0100 |
| commit | 27e7ed018113e7b96f13100787ba8c0553a63b81 (patch) | |
| tree | b740430acb2c0221b28427d416bf1e816a5a0899 /drivers/pci/controller/dwc/pcie-tegra194.c | |
| parent | PCI: dwc: Allow overriding bridge pci_ops (diff) | |
| download | wireguard-linux-27e7ed018113e7b96f13100787ba8c0553a63b81.tar.xz wireguard-linux-27e7ed018113e7b96f13100787ba8c0553a63b81.zip | |
PCI: dwc: Add a default pci_ops.map_bus for root port
The Designware root port config space is memory mapped accesses via the
DBI space by default. Add a common implementation
dw_pcie_own_conf_map_bus() for platforms to use.
Link: https://lore.kernel.org/r/20200821035420.380495-5-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-tegra194.c')
0 files changed, 0 insertions, 0 deletions