diff options
| author |   Eric Yuen <eyuen@nvidia.com> | 2014-08-26 17:11:37 +0200 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2014-09-16 16:55:33 -0600 |
| commit | ec73276204f06b6446a9c9b70173a1c15f6de536 (patch) | |
| tree | e662f3fd15fe8b9f98e7cbcde7e6bc4227a44823 /drivers/pci/host | |
| parent | PCI: tegra: Fix extended configuration space mapping (diff) | |
| download | wireguard-linux-ec73276204f06b6446a9c9b70173a1c15f6de536.tar.xz wireguard-linux-ec73276204f06b6446a9c9b70173a1c15f6de536.zip | |
PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be
pulsed. Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 6329be3d4695..79fd92c969a9 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -849,6 +849,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; pads_writel(pcie, value, soc->pads_pll_ctl); + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + usleep_range(20, 100); + /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM; |