diff options
author | 2020-03-06 14:35:47 -0600 | |
---|---|---|
committer | 2020-03-06 14:35:47 -0600 | |
commit | c20c4a084a878df35a7e394a7e646f303b505eaf (patch) | |
tree | f6aa575eb460b1d2a9600e3605b57bbdd1925d53 /drivers/perf/arm_pmu_acpi.c | |
parent | Merge branch 'akpm' (patches from Andrew) (diff) | |
parent | arm64: context: Fix ASID limit in boot messages (diff) | |
download | wireguard-linux-c20c4a084a878df35a7e394a7e646f303b505eaf.tar.xz wireguard-linux-c20c4a084a878df35a7e394a7e646f303b505eaf.zip |
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"Here are another three arm64 fixes for 5.6, all pretty minor. Main
thing is fixing a silly bug in the fsl_imx8_ddr PMU driver where we
would zero the counters when disabling them.
- Fix misreporting of ASID limit when KPTI is enabled
- Fix busted NULL pointer checks for GICC structure in ACPI PMU code
- Avoid nobbling the "fsl_imx8_ddr" PMU counters when disabling them"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: context: Fix ASID limit in boot messages
drivers/perf: arm_pmu_acpi: Fix incorrect checking of gicc pointer
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition
Diffstat (limited to 'drivers/perf/arm_pmu_acpi.c')
-rw-r--r-- | drivers/perf/arm_pmu_acpi.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c index acce8781c456..f5c7a845cd7b 100644 --- a/drivers/perf/arm_pmu_acpi.c +++ b/drivers/perf/arm_pmu_acpi.c @@ -24,8 +24,6 @@ static int arm_pmu_acpi_register_irq(int cpu) int gsi, trigger; gicc = acpi_cpu_get_madt_gicc(cpu); - if (WARN_ON(!gicc)) - return -EINVAL; gsi = gicc->performance_interrupt; @@ -64,11 +62,10 @@ static void arm_pmu_acpi_unregister_irq(int cpu) int gsi; gicc = acpi_cpu_get_madt_gicc(cpu); - if (!gicc) - return; gsi = gicc->performance_interrupt; - acpi_unregister_gsi(gsi); + if (gsi) + acpi_unregister_gsi(gsi); } #if IS_ENABLED(CONFIG_ARM_SPE_PMU) |