diff options
| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2019-02-25 16:44:45 +0000 |
|---|---|---|
| committer |   Thierry Reding <thierry.reding@gmail.com> | 2019-03-04 11:57:44 +0100 |
| commit | 74d0c3b2050927f364e3320091f234c108bd845d (patch) | |
| tree | b66ab061712ec8b2907cc36ffdcfb141421df2f5 /drivers/pwm | |
| parent | pwm: atmel: Add PWM binding for SAM9X60 (diff) | |
| download | wireguard-linux-74d0c3b2050927f364e3320091f234c108bd845d.tar.xz wireguard-linux-74d0c3b2050927f364e3320091f234c108bd845d.zip | |
pwm: atmel: Add support for SAM9X60's PWM controller
Add support for SAM9X60's PWM controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-atmel.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 4ac899d8008c..b1473ed55110 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -52,6 +52,8 @@ /* Only the LSB 16 bits are significant. */ #define PWM_MAXV1_PRD 0xFFFF +/* All 32 bits are significant. */ +#define PWM_MAXV2_PRD 0xFFFFFFFF #define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_sama5_pwm_data = { }, }; +static const struct atmel_pwm_data mchp_sam9x60_pwm_data = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, + .cfg = { + /* 32 bits to keep period and duty. */ + .max_period = PWM_MAXV2_PRD, + .max_pres = PRD_MAXV1_PRES, + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", @@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { .compatible = "atmel,sama5d2-pwm", .data = &atmel_sama5_pwm_data, }, { + .compatible = "microchip,sam9x60-pwm", + .data = &mchp_sam9x60_pwm_data, + }, { /* sentinel */ }, }; |