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| author |   Paul Cercueil <paul@crapouillou.net> | 2020-09-03 03:50:46 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-10-13 20:04:50 -0700 |
| commit | 3860dc599b7d3de869d9d7e2274d2ca8f1e2be86 (patch) | |
| tree | edf46c7e0b793b0d54983244794d7f6541c50bdb /drivers/usb/cdns3/cdns3-debug.h | |
| parent | clk: ingenic: Use readl_poll_timeout instead of custom loop (diff) | |
| download | wireguard-linux-3860dc599b7d3de869d9d7e2274d2ca8f1e2be86.tar.xz wireguard-linux-3860dc599b7d3de869d9d7e2274d2ca8f1e2be86.zip | |
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions