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| author |   Thinh Nguyen <Thinh.Nguyen@synopsys.com> | 2018-03-16 15:33:54 -0700 |
|---|---|---|
| committer |   Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-03-22 10:48:48 +0200 |
| commit | 0cab8d26d6e5e053b2bed3356992aaa71dc93628 (patch) | |
| tree | b0048a8896113650d8d03e2aeeb706531b231ebf /drivers/usb/dwc3/core.h | |
| parent | usb: dwc3: Add SoftReset PHY synchonization delay (diff) | |
| download | wireguard-linux-0cab8d26d6e5e053b2bed3356992aaa71dc93628.tar.xz wireguard-linux-0cab8d26d6e5e053b2bed3356992aaa71dc93628.zip | |
usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields
Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.
The GTXFIFOSIZ register for DWC_usb31 is as follows:
+-------+-----------+----------------------------------+
| BITS | Name | Description |
+=======+===========+==================================+
| 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address |
| 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO |
| 14:0 | TXFDEP | TXFIFO Depth |
+-------+-----------+----------------------------------+
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc3/core.h')
| -rw-r--r-- | drivers/usb/dwc3/core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 09243a680a0d..1ecdc062df58 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -255,6 +255,8 @@ #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) /* Global TX Fifo Size Register */ +#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ +#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */ #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |