diff options
| author |   Thinh Nguyen <thinh.nguyen@synopsys.com> | 2018-11-07 17:55:13 -0800 |
|---|---|---|
| committer |   Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-11-26 09:06:31 +0200 |
| commit | 62ba09d6bb6330d8a70e40e23891d8764663d469 (patch) | |
| tree | 1a4ca0d85190f6cf118ab2e7b0615057ccf44034 /drivers/usb/dwc3/core.h | |
| parent | usb: dwc3: debugfs: Print eps Tx/RxFIFO in bytes (diff) | |
| download | wireguard-linux-62ba09d6bb6330d8a70e40e23891d8764663d469.tar.xz wireguard-linux-62ba09d6bb6330d8a70e40e23891d8764663d469.zip | |
usb: dwc3: debugfs: Dump internal LSP and ep registers
To dump internal LSP and endpoint state debug registers, we must write
to GDBGLSPMUX register. This patch correctly dump LSP and endpoint
states from the debug registers.
If the controller is in device mode, all LSP and endpoint state
registers will be dumped via the debugfs attribute "lsp_dump". In host
mode, the user has to write the LSP number to "lsp_dump" to dump a
specific LSP selection.
Fixes: 80b776340c78 ("usb: dwc3: Dump LSP and BMU debug info")
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc3/core.h')
| -rw-r--r-- | drivers/usb/dwc3/core.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 2ba034b5da07..7b17bb6a353c 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -174,6 +174,12 @@ #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff +/* Global Debug LSP MUX Select */ +#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ +#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) +#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) +#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) + /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) @@ -253,6 +259,9 @@ #define DWC3_GSTS_DEVICE_IP BIT(6) #define DWC3_GSTS_CSR_TIMEOUT BIT(5) #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) +#define DWC3_GSTS_CURMOD(n) ((n) & 0x3) +#define DWC3_GSTS_CURMOD_DEVICE 0 +#define DWC3_GSTS_CURMOD_HOST 1 /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) @@ -321,6 +330,7 @@ #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) +#define DWC3_GHWPARAMS1_ENDBC BIT(31) /* Global HWPARAMS3 Register */ #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) @@ -945,6 +955,7 @@ struct dwc3_scratchpad_array { * @hwparams: copy of hwparams registers * @root: debugfs root folder pointer * @regset: debugfs pointer to regdump file + * @dbg_lsp_select: current debug lsp mux register selection * @test_mode: true when we're entering a USB test mode * @test_mode_nr: test feature selector * @lpm_nyet_threshold: LPM NYET response threshold @@ -1121,6 +1132,8 @@ struct dwc3 { struct dentry *root; struct debugfs_regset32 *regset; + u32 dbg_lsp_select; + u8 test_mode; u8 test_mode_nr; u8 lpm_nyet_threshold; |