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| author |   Ralf Baechle <ralf@linux-mips.org> | 2005-03-02 19:18:46 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:50 +0100 |
| commit | 88d535b6b58632bc51ee9a1f35ddfc357e365c37 (patch) | |
| tree | 4b828339622e86b4809772120b2357239ef3c676 /include/asm-mips/hazards.h | |
| parent | Sparseify MIPS. (diff) | |
| download | wireguard-linux-88d535b6b58632bc51ee9a1f35ddfc357e365c37.tar.xz wireguard-linux-88d535b6b58632bc51ee9a1f35ddfc357e365c37.zip | |
One definition of back_to_back_c0_hazard too much.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/hazards.h')
| -rw-r--r-- | include/asm-mips/hazards.h | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d6e88cf06ba9..181f08de889c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -107,6 +107,7 @@ __asm__( " .endm \n\t"); #ifdef CONFIG_CPU_RM9000 + /* * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent * use of the JTLB for instructions should not occur for 4 cpu cycles and use @@ -144,12 +145,6 @@ __asm__( "nop; nop; nop; nop; nop; nop;\n\t" \ ".set reorder\n\t") -#define back_to_back_c0_hazard() \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " nop; nop; nop \n" \ - " .set reorder \n") - #endif /* |