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| author |   Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2019-03-06 22:48:35 +0200 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2019-03-28 06:12:42 +0200 |
| commit | 00d082cc4ea6e42ec4fed832a1020231bb1ca150 (patch) | |
| tree | 6b2257d90fee778e56f93003a7fab563d4536fec /include/drm/drm_fb_helper.h | |
| parent | drm: rcar-du: lvds: Adjust operating frequency for D3 and E3 (diff) | |
| download | wireguard-linux-00d082cc4ea6e42ec4fed832a1020231bb1ca150.tar.xz wireguard-linux-00d082cc4ea6e42ec4fed832a1020231bb1ca150.zip | |
drm: rcar-du: lvds: Set LVEN and LVRES bits together on D3
On the D3 SoC the LVDS PHY must be enabled in the same register write
that enables the LVDS output. Skip writing the LVEN bit independently
on that platform, it will be set by the write that sets LVRES.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Diffstat (limited to 'include/drm/drm_fb_helper.h')
0 files changed, 0 insertions, 0 deletions