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| author |   Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-03-09 15:36:35 +0800 |
|---|---|---|
| committer |   Robert Foss <robert.foss@linaro.org> | 2022-03-09 14:14:36 +0100 |
| commit | 1498915233dde830061e008ad639b482fd76f93d (patch) | |
| tree | 09d4aee61b4e25fbed8c684266a48f3522449b67 /include/drm/drm_mipi_dsi.h | |
| parent | dt-bindings: display: sitronix, st7735r: Remove spi-max-frequency limit (diff) | |
| download | wireguard-linux-1498915233dde830061e008ad639b482fd76f93d.tar.xz wireguard-linux-1498915233dde830061e008ad639b482fd76f93d.zip | |
drm/dsi: transfer DSI HS packets ending at the same time
Since a HS transmission is composed of an arbitrary number
of bytes that may not be an integer multiple of lanes, some
lanes may run out of data before others.
(Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)
However, for some DSI RX devices (for example, anx7625),
there is a limitation that packet number should be the same
on all DSI lanes. In other words, they need to end a HS at
the same time.
Because this limitation is for some specific DSI RX devices,
it is more reasonable to put the enable control in these
DSI RX drivers. If DSI TX driver knows the information,
they can adjust the setting for this situation.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309073637.3591-2-rex-bc.chen@mediatek.com
Diffstat (limited to 'include/drm/drm_mipi_dsi.h')
| -rw-r--r-- | include/drm/drm_mipi_dsi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 147e51b6d241..51e09a1a106a 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -137,6 +137,8 @@ struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node); #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) /* transmit data in low power */ #define MIPI_DSI_MODE_LPM BIT(11) +/* transmit data ending at the same time for all lanes within one hsync */ +#define MIPI_DSI_HS_PKT_END_ALIGNED BIT(12) enum mipi_dsi_pixel_format { MIPI_DSI_FMT_RGB888, |