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| author |   Icenowy Zheng <icenowy@aosc.io> | 2019-05-21 18:10:59 +0200 |
|---|---|---|
| committer |   Rob Herring <robh@kernel.org> | 2019-05-22 14:19:59 -0500 |
| commit | d4db6c089099d38166752c93d9d165fb7526f1e5 (patch) | |
| tree | fd476cfcd3634589b764a77be84767345f153252 /include/drm/drm_mode_config.h | |
| parent | drm: remove prime sg_table caching (diff) | |
| download | wireguard-linux-d4db6c089099d38166752c93d9d165fb7526f1e5.tar.xz wireguard-linux-d4db6c089099d38166752c93d9d165fb7526f1e5.zip | |
dt-bindings: gpu: add bus clock for Mali Midgard GPUs
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190521161102.29620-4-peron.clem@gmail.com
Diffstat (limited to 'include/drm/drm_mode_config.h')
0 files changed, 0 insertions, 0 deletions