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| author |   Animesh Manna <animesh.manna@intel.com> | 2020-03-16 16:07:59 +0530 |
|---|---|---|
| committer |   Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2020-04-08 14:41:09 +0200 |
| commit | 8cdf727119289db3a98835662eb28e1c5ad835f1 (patch) | |
| tree | 83c7d5a4aa3a04c1cbafe933ca38e49aa46971ec /include/drm | |
| parent | drm/i915/dp: Register definition for DP compliance register (diff) | |
| download | wireguard-linux-8cdf727119289db3a98835662eb28e1c5ad835f1.tar.xz wireguard-linux-8cdf727119289db3a98835662eb28e1c5ad835f1.zip | |
drm/i915/dp: Program vswing, pre-emphasis, test-pattern
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
v1: Initial patch.
v2: Fixes added during testing with test-scope. (Khaled/Clint/Manasi)
- pipe used as argument during registers programming instead of port.
- TRANS_CONF must be disable/enable as well during ddi disable/enable.
- harcoded PLTPAT 80 bit custom pattern as the DPR-100 does not set it
in the sink’s DPCDs
- TRANS_DDI_FUNC_CTL DDI_Select (Bits 27:30) need to reset/set during
disable/enable.
v3: used macros instead of numbers and some cosmetic changes. [Manasi]
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200316103759.12867-8-animesh.manna@intel.com
Diffstat (limited to 'include/drm')
0 files changed, 0 insertions, 0 deletions