diff options
| author |   Andrew Bresticker <abrestic@chromium.org> | 2013-09-25 14:12:51 -0700 |
|---|---|---|
| committer |   Tomasz Figa <t.figa@samsung.com> | 2014-01-08 18:02:43 +0100 |
| commit | 3538a2cf0e04ad69840d74f46f7f8af920d913b5 (patch) | |
| tree | f01c90bdb68d818038b67d06aee0a86e0c4b0247 /include/dt-bindings/clk | |
| parent | ARM: dts: exynos5250: add input clocks to audss clock controller (diff) | |
| download | wireguard-linux-3538a2cf0e04ad69840d74f46f7f8af920d913b5.tar.xz wireguard-linux-3538a2cf0e04ad69840d74f46f7f8af920d913b5.zip | |
clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings/clk')
| -rw-r--r-- | include/dt-bindings/clk/exynos-audss-clk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f427c60f..0ae6f5a75d2a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif |