diff options
| author |   Yakir Yang <ykk@rock-chips.com> | 2016-02-24 18:14:25 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2016-02-26 01:53:35 +0100 |
| commit | 2d2671ea4b35454b30a69744ce258489920e4d2b (patch) | |
| tree | 098339384a97352079344fa37648d71a6cf19b23 /include/dt-bindings/clock/rk3228-cru.h | |
| parent | clk: rockchip: add the new clock ids for RK3228 VOP (diff) | |
| download | wireguard-linux-2d2671ea4b35454b30a69744ce258489920e4d2b.tar.xz wireguard-linux-2d2671ea4b35454b30a69744ce258489920e4d2b.zip | |
clk: rockchip: add the new clock ids for RK3228 HDMI
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/dt-bindings/clock/rk3228-cru.h')
| -rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 9ce3da8b51c3..5d43ed9b05ad 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -51,9 +51,11 @@ #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 /* dclk gates */ #define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 /* aclk gates */ #define ACLK_DMAC 194 @@ -78,6 +80,8 @@ #define PCLK_PWM 350 #define PCLK_TIMER 353 #define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 /* hclk gates */ #define HCLK_VOP 452 |