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authorThierry Reding <treding@nvidia.com>2017-06-26 17:33:12 +0200
committerThierry Reding <treding@nvidia.com>2017-12-13 12:42:30 +0100
commitf580fd3f9d78cf0425ab98950796c578d8a82167 (patch)
tree5ab1276160226e5cae7291f12c822fcb9bec656a /include/dt-bindings/memory
parentLinux 4.15-rc1 (diff)
downloadwireguard-linux-f580fd3f9d78cf0425ab98950796c578d8a82167.tar.xz
wireguard-linux-f580fd3f9d78cf0425ab98950796c578d8a82167.zip
dt-bindings: misc: Add Tegra186 MISC registers bindings
The MISC register block found on Tegra186 SoCs contains registers that can be used to identify a given chip and various strapping options. Signed-off-by: Thierry Reding <treding@nvidia.com>
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