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| author |   Álvaro Fernández Rojas <noltari@gmail.com> | 2020-06-17 12:50:39 +0200 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-11-17 21:53:03 +0100 |
| commit | 7acf84e87857721d66a1ba800c2c50669089f43d (patch) | |
| tree | 6b644c6cc10cf66ed9a05502b8469f7e557908e2 /include/dt-bindings/reset | |
| parent | mips: bmips: dts: add BCM6362 reset controller support (diff) | |
| download | wireguard-linux-7acf84e87857721d66a1ba800c2c50669089f43d.tar.xz wireguard-linux-7acf84e87857721d66a1ba800c2c50669089f43d.zip | |
mips: bmips: dts: add BCM6368 reset controller support
BCM6368 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/bcm6368-reset.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h new file mode 100644 index 000000000000..c81d8eb6d173 --- /dev/null +++ b/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */ |