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| author |   Stephen Boyd <sboyd@kernel.org> | 2024-11-06 13:30:22 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-11-06 13:30:22 -0800 |
| commit | 0c159634c9a0c8836948893cfc27586ef2b73696 (patch) | |
| tree | da5ccc0ec95ba2813e67513689e66b7138d166fe /include/dt-bindings | |
| parent | Merge tag 'renesas-clk-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas (diff) | |
| parent | clk: renesas: vbattb: Add VBATTB clock driver (diff) | |
| download | wireguard-linux-0c159634c9a0c8836948893cfc27586ef2b73696.tar.xz wireguard-linux-0c159634c9a0c8836948893cfc27586ef2b73696.zip | |
Merge tag 'renesas-clk-for-v6.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add RTC power domain and Battery Backup Function (VBATTB) clock
support for the Renesas RZ/G3S SoC
- Add the devm_clk_hw_register_gate_parent_hw() helper
* tag 'renesas-clk-for-v6.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: vbattb: Add VBATTB clock driver
clk: Add devm_clk_hw_register_gate_parent_hw()
clk: renesas: rzg2l: Fix FOUTPOSTDIV clk
dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
clk: renesas: r9a08g045: Add power domain for RTC
clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe
clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones
clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()
dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/r9a08g045-cpg.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a08g045-vbattb.h | 13 |
2 files changed, 14 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h index 8281e9caf3a9..311521fe4b59 100644 --- a/include/dt-bindings/clock/r9a08g045-cpg.h +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -308,5 +308,6 @@ #define R9A08G045_PD_DDR 64 #define R9A08G045_PD_TZCDDR 65 #define R9A08G045_PD_OTFDE_DDR 66 +#define R9A08G045_PD_RTC 67 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ |