diff options
| author |   Damien Le Moal <damien.lemoal@wdc.com> | 2020-03-16 09:47:41 +0900 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2020-04-03 10:50:15 -0700 |
| commit | 5ba568f57f0ae4826beb6aaeecb12e68219b8a0b (patch) | |
| tree | 75a83dcbc8a697d89eb47e15861a7088c582fa72 /include/dt-bindings | |
| parent | riscv: Select required drivers for Kendryte SOC (diff) | |
| download | wireguard-linux-5ba568f57f0ae4826beb6aaeecb12e68219b8a0b.tar.xz wireguard-linux-5ba568f57f0ae4826beb6aaeecb12e68219b8a0b.zip | |
riscv: Add Kendryte K210 device tree
Add a generic device tree for Kendryte K210 SoC based boards. This is
for now a very simple device tree describing the core elements of the
SoC. This is suitable (and tested) for the Kendryte KD233 development
board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/k210-clk.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h new file mode 100644 index 000000000000..5a2fd64d1a49 --- /dev/null +++ b/include/dt-bindings/clock/k210-clk.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef K210_CLK_H +#define K210_CLK_H + +/* + * Arbitrary identifiers for clocks. + * The structure is: in0 -> pll0 -> aclk -> cpu + * + * Since we use the hardware defaults for now, set all these to the same clock. + */ +#define K210_CLK_PLL0 0 +#define K210_CLK_PLL1 0 +#define K210_CLK_ACLK 0 +#define K210_CLK_CPU 0 + +#endif /* K210_CLK_H */ |