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| author |   Shawn Guo <shawn.guo@linaro.org> | 2016-07-08 17:00:39 +0800 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-08-31 15:24:23 +0200 |
| commit | 0e125a5facf857567f8bb6dbb1ceefac14b2fa64 (patch) | |
| tree | cbcbae8813c7018412c576978248113360f93148 /include/linux/amba | |
| parent | Linux 4.8-rc2 (diff) | |
| download | wireguard-linux-0e125a5facf857567f8bb6dbb1ceefac14b2fa64.tar.xz wireguard-linux-0e125a5facf857567f8bb6dbb1ceefac14b2fa64.zip | |
tty: amba-pl011: define flag register bits for ZTE device
For some reason we do not really understand, ZTE hardware designers
choose to define PL011 Flag Register bit positions differently from
standard ones as below.
Bit Standard ZTE
-----------------------------------
CTS 0 1
DSR 1 3
BUSY 3 8
RI 8 0
Let's define these bits into vendor data and get ZTE PL011 supported
properly.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/amba')
| -rw-r--r-- | include/linux/amba/serial.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h index d76a19ba2cff..ad0965e21a5e 100644 --- a/include/linux/amba/serial.h +++ b/include/linux/amba/serial.h @@ -104,6 +104,15 @@ #define UART01x_FR_CTS 0x001 #define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) +/* + * Some bits of Flag Register on ZTE device have different position from + * standard ones. + */ +#define ZX_UART01x_FR_BUSY 0x100 +#define ZX_UART01x_FR_DSR 0x008 +#define ZX_UART01x_FR_CTS 0x002 +#define ZX_UART011_FR_RI 0x001 + #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */ #define UART011_CR_OUT2 0x2000 /* OUT2 */ |