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authorGustavo Sousa <gustavo.sousa@intel.com>2026-05-14 18:44:44 -0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2026-05-18 09:22:35 -0400
commit16be14eec5fdaea9477368856a85173246c41454 (patch)
treeea91fc175b9c19a35fabc227032569d6a12ebb66 /include/linux/bcma/ssh:/git@git.zx2c4.com
parentdrm/xe/pf: Fix CFI failure in debugfs access (diff)
drm/xe: Define CACHE_MODE_1 as MCR register
CACHE_MODE_1 is a MCR register for all platforms that currently use it in the Xe driver. Use XE_REG_MCR() when defining it. Fixes: 8cd7e9759766 ("drm/xe: Add missing DG2 lrc workarounds") Fixes: ff063430caa8 ("drm/xe/mtl: Add some initial MTL workarounds") Bspec: 66534, 67788 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-1-30dd47855fee@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> (cherry picked from commit 8f765f0c054e0fb39980a76b4c899b027395929d) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'include/linux/bcma/ssh:/git@git.zx2c4.com')
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