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| author |   Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-01-14 09:17:44 +0800 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2026-01-15 10:04:26 +0100 |
| commit | 4e955c08d6dc76fb60cda9af955ddcebedaa7f69 (patch) | |
| tree | 23fb1dc3d482b63418d1c249ed66007f293067c1 /include/linux/bcma/ssh:/git@git.zx2c4.com | |
| parent | perf/core: Fix slow perf_event_task_exit() with LBR callstacks (diff) | |
perf/x86/intel: Support the 4 new OMR MSRs introduced in DMR and NVL
Diamond Rapids (DMR) and Nova Lake (NVL) introduce an enhanced
Off-Module Response (OMR) facility, replacing the Off-Core Response (OCR)
Performance Monitoring of previous processors.
Legacy microarchitectures used the OCR facility to evaluate off-core and
multi-core off-module transactions. The newly named OMR facility improves
OCR capabilities for scalable coverage of new memory systems in
multi-core module systems.
Similar to OCR, 4 additional off-module configuration MSRs
(OFFMODULE_RSP_0 to OFFMODULE_RSP_3) are introduced to specify attributes
of off-module transactions. When multiple identical OMR events are
created, they need to occupy the same OFFMODULE_RSP_x MSR. To ensure
these multiple identical OMR events can work simultaneously, the
intel_alt_er() and intel_fixup_er() helpers are enhanced to rotate these
OMR events across different OFFMODULE_RSP_* MSRs, similar to previous OCR
events.
For more details about OMR, please refer to section 16.1 "OFF-MODULE
RESPONSE (OMR) FACILITY" in ISE documentation.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260114011750.350569-2-dapeng1.mi@linux.intel.com
Diffstat (limited to 'include/linux/bcma/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions