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| author |   Weihao Li <cn.liweihao@gmail.com> | 2023-10-31 19:18:16 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-11-16 21:26:43 +0100 |
| commit | c6c5a5580dcb6631aa6369dabe12ef3ce784d1d2 (patch) | |
| tree | 543ac229904ff88529dd9b4e17057b16f4c3214b /include/linux/bcma/ssh:/git@git.zx2c4.com | |
| parent | clk: rockchip: rk3568: Add PLL rate for 292.5MHz (diff) | |
clk: rockchip: rk3128: Fix HCLK_OTG gate register
The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON.
Signed-off-by: Weihao Li <cn.liweihao@gmail.com>
Link: https://lore.kernel.org/r/20231031111816.8777-1-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/linux/bcma/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions