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| author | 2025-10-27 18:33:33 +0800 | |
|---|---|---|
| committer | 2025-10-27 12:17:05 +0000 | |
| commit | d914ec6f07548f7c13a231a4f526e043e736e82e (patch) | |
| tree | fd018347e60960c65b4825fc8558a7181196a0c6 /include/linux/ceph/git:/ssh:/git@git.zx2c4.com | |
| parent | ASoC: fsl: correct the bit order issue for DSD (diff) | |
| download | wireguard-linux-d914ec6f07548f7c13a231a4f526e043e736e82e.tar.xz wireguard-linux-d914ec6f07548f7c13a231a4f526e043e736e82e.zip | |
ASoC: rt721: fix prepare clock stop failed
This patch adds settings to prevent the 'prepare clock stop failed' error.
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://patch.msgid.link/20251027103333.38353-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/ceph/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions
