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| author |   Jonas Gorski <jonas.gorski@gmail.com> | 2019-04-18 13:12:04 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-04-23 10:57:48 -0700 |
| commit | 434d69fad63b443d7afc8aa99264359c9b4e2d3a (patch) | |
| tree | 5608c21f98cfa92b2ba138498bf48b4015e9e42d /include/linux/clk-provider.h | |
| parent | Linux 5.1-rc1 (diff) | |
| download | wireguard-linux-434d69fad63b443d7afc8aa99264359c9b4e2d3a.tar.xz wireguard-linux-434d69fad63b443d7afc8aa99264359c9b4e2d3a.zip | |
clk: divider: add explicit big endian support
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian divider clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/linux/clk-provider.h')
| -rw-r--r-- | include/linux/clk-provider.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b7cf80a71293..f0abdfbe3d60 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -417,6 +417,9 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used + * for the divider register. Setting this flag makes the register accesses + * big endian. */ struct clk_divider { struct clk_hw hw; @@ -438,6 +441,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_BIG_ENDIAN BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; |