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| author |   Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-21 09:06:43 +0200 |
|---|---|---|
| committer |   Miquel Raynal <miquel.raynal@bootlin.com> | 2019-06-27 20:05:30 +0200 |
| commit | ef347c0cfd619a9251e5a2f9ff72e33650a9bccb (patch) | |
| tree | 56fc6f1c9fd9763d53c57dd97f64ab295fc54c69 /include/linux/dma | |
| parent | dmaengine: mxs: rename custom flag (diff) | |
| download | wireguard-linux-ef347c0cfd619a9251e5a2f9ff72e33650a9bccb.tar.xz wireguard-linux-ef347c0cfd619a9251e5a2f9ff72e33650a9bccb.zip | |
mtd: rawnand: gpmi: Implement exec_op
The gpmi driver performance suffers from NAND operations being split
in multiple small DMA transfers. This has been forced by the NAND layer
in the former days, but now with exec_op we can use the controller as
intended.
With this patch gpmi_nfc_exec_op becomes the main entry point to NAND
operations. Here all instructions are collected and chained as separate
DMA transfers. In the end whole chain is fired and waited to be
finished. gpmi_nfc_exec_op only does the hardware operations, bad block
marker swapping and buffer scrambling is done by the callers. It's worth
noting that the nand_*_op functions always take the buffer lengths for
the data that the NAND chip actually transfers. When doing BCH we have
to calculate the net data size from the raw data size in some places.
This patch has been tested with 2048/64 and 2048/128 byte NAND on
i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without
errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests
from mtdutils run without errors and UBIFS can successfully be mounted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'include/linux/dma')
| -rw-r--r-- | include/linux/dma/mxs-dma.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/dma/mxs-dma.h b/include/linux/dma/mxs-dma.h index 4a33f2c8a682..069d9f5a609e 100644 --- a/include/linux/dma/mxs-dma.h +++ b/include/linux/dma/mxs-dma.h @@ -5,6 +5,7 @@ #include <linux/dmaengine.h> #define MXS_DMA_CTRL_WAIT4END BIT(31) +#define MXS_DMA_CTRL_WAIT4RDY BIT(30) /* * The mxs dmaengine can do PIO transfers. We pass a pointer to the PIO words |