diff options
| author |   Matt Roper <matthew.d.roper@intel.com> | 2026-04-10 15:50:30 -0700 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2026-04-29 11:28:17 -0400 |
| commit | 9407936237c98104873550219efedc286f28bbe9 (patch) | |
| tree | d334b23408c8cdd7e8d095c9ee194cdef3724846 /include/linux/hsi/ssh:/git@git.zx2c4.com | |
| parent | drm/xe/tuning: Use proper register offset for GAMSTLB_CTRL (diff) | |
drm/xe: Mark ROW_CHICKEN5 as a masked register
ROW_CHICKEN5 is a masked register (i.e., to adjust the value of any of
the lower 16 bits, the corresponding bit in the upper 16 bits must also
be set). Add the XE_REG_OPTION_MASKED to its definition; failure to do
so will cause workaround updates of this register to not apply properly.
Bspec: 56853
Fixes: 835cd6cbb0d0 ("drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10")
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-3-e206a62ee38f@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit cd84bfbba7feb4c1e72356f14de026dfda1a9e2a)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'include/linux/hsi/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions