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| author |   Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 03:55:41 +0000 |
|---|---|---|
| committer |   Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-24 13:47:32 +1100 |
| commit | 2319f1239592d0de80414ad2338c2bd7384a2a41 (patch) | |
| tree | 805de041dfc84ae9ca767c9767d833977654dbe0 /include/linux/interrupt.h | |
| parent | powerpc/mm: Used free register to save a few cycles in SW TLB miss handling (diff) | |
| download | wireguard-linux-2319f1239592d0de80414ad2338c2bd7384a2a41.tar.xz wireguard-linux-2319f1239592d0de80414ad2338c2bd7384a2a41.zip | |
powerpc/mm: e300c2/c3/c4 TLB errata workaround
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Based on patch from David Jander <david@protonic.nl>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include/linux/interrupt.h')
0 files changed, 0 insertions, 0 deletions