diff options
| author |   Jungseung Lee <js07.lee@samsung.com> | 2020-03-18 21:06:14 +0900 |
|---|---|---|
| committer |   Tudor Ambarus <tudor.ambarus@microchip.com> | 2020-03-24 11:47:42 +0200 |
| commit | 05635c14a292de0e1a221dc31c04aba3913f03c8 (patch) | |
| tree | 0ba072883421d983b78f4d99c381d834093911fb /include/linux/mtd | |
| parent | mtd: spi-nor: Add generic formula for SR block protection handling (diff) | |
| download | wireguard-linux-05635c14a292de0e1a221dc31c04aba3913f03c8.tar.xz wireguard-linux-05635c14a292de0e1a221dc31c04aba3913f03c8.zip | |
mtd: spi-nor: Add SR 4bit block protection support
Currently we are supporting block protection only for flash chips with
3 block protection bits (BP0-2) in the SR register.
Enable block protection support for flashes with 4 block protection bits
(BP0-3).
Add a flash_info flag for flashes that describe 4 block protection bits.
Add another flash_info flag for flashes in which BP3 bit is not adjacent
to the BP0-2 bits.
Tested with a n25q512ax3 (BP0-3) and w25q128 (BP0-2).
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e656858b50a5..1e2af0ec1f03 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -111,7 +111,9 @@ #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ +#define SR_BP3 BIT(5) /* Block protect 3 */ #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ +#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */ #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ #define SR_SRWD BIT(7) /* SR write protect */ /* Spansion/Cypress specific status bits */ |