diff options
| author |   Sagar Shrikant Kadam <sagar.kadam@sifive.com> | 2019-10-22 17:22:19 +0000 |
|---|---|---|
| committer |   Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-11 20:42:55 +0200 |
| commit | 83cba933a6db1dd4d7ac85170f99461fbc339eff (patch) | |
| tree | 16106b667dd65804efdd92dd56ac1a47c650bbb9 /include/linux/mtd | |
| parent | mtd: spi-nor: Add support for is25wp256 (diff) | |
| download | wireguard-linux-83cba933a6db1dd4d7ac85170f99461fbc339eff.tar.xz wireguard-linux-83cba933a6db1dd4d7ac85170f99461fbc339eff.zip | |
mtd: spi-nor: Set default Quad Enable method for ISSI flashes
Set the default Quad Enable method for ISSI flashes. Used for
ISSI flashes (IS25WP256D-JMLE) that do not support SFDP tables
and can not determine the Quad Enable method by parsing BFPT.
Based on code originally written by Wesley Terpstra <wesley@sifive.com>
and/or Palmer Dabbelt <palmer@sifive.com>
https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
[tudor.ambarus@microchip.com:
- rebase, split and adapt for latest spi-nor/next,
- use PMC CFI ID for ISSI. According to JEP106BA, "Programmable Micro Corp"
changed its name to Integrated Silicon Solution (ISSI)]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9eae35c60bce..5a4623fc586b 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -22,6 +22,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ +#define SNOR_MFR_ISSI CFI_MFR_PMC #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST |