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| author |   Peter Chen <peter.chen@freescale.com> | 2015-03-17 17:32:45 +0800 |
|---|---|---|
| committer | Peter Chen <peter.chen@freescale.com> | 2015-08-14 10:03:58 +0800 |
| commit | 96625eadca1bb8832fb502f0899a543695f1ba35 (patch) | |
| tree | f9f14300d30bcf9bf0b3b830838bb66e26566741 /include/linux/usb/chipidea.h | |
| parent | Doc: usb: ci-hdrc-usb2: add tx(rx)-burst-config-dword for binding doc (diff) | |
| download | wireguard-linux-96625eadca1bb8832fb502f0899a543695f1ba35.tar.xz wireguard-linux-96625eadca1bb8832fb502f0899a543695f1ba35.zip | |
usb: chipidea: add tx/rx burst size configuration interface
The user can adjust it through dts or platform data
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'include/linux/usb/chipidea.h')
| -rw-r--r-- | include/linux/usb/chipidea.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index cd7fcad49017..575eaf0ebac1 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -34,6 +34,8 @@ struct ci_hdrc_platform_data { #define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7) #define CI_HDRC_SET_NON_ZERO_TTHA BIT(8) #define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) +#define CI_HDRC_OVERRIDE_TX_BURST BIT(10) +#define CI_HDRC_OVERRIDE_RX_BURST BIT(11) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 @@ -43,6 +45,8 @@ struct ci_hdrc_platform_data { /* interrupt threshold setting */ u32 itc_setting; u32 ahb_burst_config; + u32 tx_burst_size; + u32 rx_burst_size; }; /* Default offset of capability registers */ |