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| author |   Marc Zyngier <maz@kernel.org> | 2022-05-04 16:09:47 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-05-04 16:09:47 +0100 |
| commit | a6ad8551b86137cbe266cbbeb512ee550ba3af6e (patch) | |
| tree | 51d73410f06c9d0be46aff4418dead74fbc5c43d /include/linux | |
| parent | Merge branch irq/gpio-immutable into irq/irqchip-next (diff) | |
| parent | irqchip/gic-v3: Claim iomem resources (diff) | |
| download | wireguard-linux-a6ad8551b86137cbe266cbbeb512ee550ba3af6e.tar.xz wireguard-linux-a6ad8551b86137cbe266cbbeb512ee550ba3af6e.zip | |
Merge branch irq/gic-v3-5.19 into irq/irqchip-next
* irq/gic-v3-5.19:
: .
: Misc improvements for GICv3:
:
: - Minimise the number of cases where we need to poll RWP
:
: - Allow the use of MMIO-based invalidation for LPIs
:
: - Track GICD/GICR mappings in /proc/iomem
:
: - Tighten the GICv3 DT binding to avoid endless discussions
: on the list...
: .
irqchip/gic-v3: Claim iomem resources
dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit
irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP
irqchip/gic-v3: Detect LPI invalidation MMIO registers
irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 12d91f0dedf9..728691365464 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -127,6 +127,8 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_CES (1UL << 1) +#define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) |